The known jitter reduction circuit to reduce phase noise in a pulse train comprises:                a resettable integrator to integrate the pulse train,        a comparator to compare the integrated pulse train with a reference level and to generate a modified pulse train with reduced phase noise,        
An example of such a jitter reduction circuit is described in WO 97/30516 in the name of UNDERHILL, Michael et al.
A known jitter reduction circuit continuously integrates the pulse train to obtain an analog sawtooth signal. The integration process is not perfect because of the use of capacitors and other electronic analog components. For example, if in one cycle, a capacitor is first charged from a voltage VA to a voltage VB with a current IA and then discharged from voltage VB to VA with a current −IA to generate one tooth of the sawtooth signal, an integration error appears. In fact, the time necessary to charge the capacitor from voltage VA to voltage VB is not exactly the same as the one necessary to discharge the same capacitor from voltage VB to voltage VA. The integration error is small for one cycle. However, in known jitter reduction circuits, the integration error is accumulated from one cycle to the next one so that the accumulated integration error grows more and more important. Thus, these jitter reduction circuits are unreliable.